INTEGRATED CIRCUIT LAYOUT GENERATION METHOD
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United States of America Patent
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Issued Date -
May 16, 2024
app pub date -
Jan 24, 2024
filing date -
May 2, 2018
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Abstract
A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
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