MEMORY SYSTEM WITH CACHED MEMORY MODULE OPERATIONS
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United States of America Patent
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Issued Date -
May 16, 2024
app pub date -
Nov 17, 2023
filing date -
Oct 1, 2015
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Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
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