DUTY-CYCLE CORRECTOR CIRCUIT
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United States of America Patent
Stats
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N/A
Issued Date -
May 9, 2024
app pub date -
Jan 16, 2024
filing date -
May 6, 2021
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
First Claim
Other Claims data not available