METHOD AND CIRCUIT FOR DLL LOCKING MECHANISM FOR WIDE RANGE HARMONIC DETECTION AND FALSE LOCK DETECTION
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United States of America Patent
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Issued Date -
May 2, 2024
app pub date -
Mar 31, 2023
filing date -
Nov 2, 2022
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status (Latency Note)
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Abstract
A circuit includes a phase detector configured to produce a first up signal and a first down signal based on a difference between a reference clock and a feedback clock and a harmonic detector coupled to the phase detector, the harmonic detector configured to produce a second up signal based on the first up signal and whether the harmonic detector detects a harmonic lock between the reference clock and the feedback clock based on a first clock phase and a second clock phase. Additionally, the circuit includes a false lock detector coupled to the phase detector and to the harmonic detector, the false lock detector configured to produce a second down signal based on the first down signal and whether the false lock detector detects a false lock between the reference clock and the feedback clock based on a third clock phase and a fourth clock phase.
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