CLOCK MANAGEMENT APPARATUS, CLOCK FREQUENCY DIVISION MODULE AND SYSTEM-ON-CHIP
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
May 2, 2024
app pub date -
Dec 31, 2021
filing date -
Feb 25, 2021
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
Provided is a clock management apparatus wherein the clock management apparatus includes a clock synchronization signal generator, a plurality of clock gating units and clock frequency division modules; a synchronization signal of a predetermined period is generated by the clock synchronization signal generator; each of the clock gating units is connected in series with a corresponding one of the clock frequency division modules to form a signal processing branch; and the signal processing branches are connected in parallel to receive a source clock signal respectively, the clock gating unit controls the on-off switch of the signal processing branch, and the clock frequency division modules are configured to perform phase adjustment on the clock signals of the signal processing branches after receiving the synchronization signal output by the clock synchronization signal generator, and to adjust the clock signals of the signal processing branches from an asynchronous state to a synchronous state.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully