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United States of America Patent

APP PUB NO 20240145603A1
SERIAL NO

18408001

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Abstract

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An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

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Patent Owner(s)

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TEXAS INSTRUMENTS INCORPORATEDDALLAS TX

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Jingjing Santa Clara, US 58 60
Guo, Honglin Dallas, US 29 64
Lee, Zachary K Fremont, US 23 226

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3335716251501 - 1011 - 20020004000600080001000012000140001600018000200002200024000260002800030000320003400036000

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