PROGRAMMABLE PROCESSING ARRAY SUPPORTING MULTI-DIMENSIONAL INTERPOLATION COMPUTATIONS
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United States of America Patent
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Issued Date -
Apr 25, 2024
app pub date -
Dec 8, 2023
filing date -
Dec 8, 2023
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Abstract
Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.
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