CONTROL CIRCUIT AND MEMORY
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United States of America Patent
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Issued Date -
Apr 18, 2024
app pub date -
Aug 16, 2023
filing date -
Oct 12, 2022
priority date (Note) -
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status (Latency Note)
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Abstract
A control circuit is provided, including a random module and an output module. A first input terminal of the random module receives a refresh count signal, a second input terminal receives random data, and a control terminal is connected to an output terminal of the output module. The random module processes the refresh count signal and the random data based on a row hammer refresh (RHR) signal output by the output module to obtain and output a random signal. A first input terminal of the output module receives the refresh count signal, a second input terminal is connected to an output terminal of the random module. The output module generates and outputs the RHR signal according to the random signal and the refresh count signal.
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