Dual digital phase lock loop with unmodulation coupling
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United States of America Patent
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Jun 18, 2024
Grant Date -
Apr 11, 2024
app pub date -
Oct 7, 2022
filing date -
Oct 7, 2022
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Abstract
Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.
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