COMPOSITE GATE DIELECTRIC FOR HIGH-VOLTAGE DEVICE
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Apr 4, 2024
app pub date -
Jan 5, 2023
filing date -
Oct 4, 2022
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully