GALVANIC ISOLATION DEVICE

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United States of America Patent

APP PUB NO 20240113094A1
SERIAL NO

17957847

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Abstract

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A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENTS INCPO BOX 655474 M/S 3999 DALLAS TX 75265

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barot, Kashyap Bangalore, IN 13 4
Bonifield, Thomas Dyer Dallas, US 44 143
S, Sreeram N Bangalore, IN 8 51
Stewart, Elizabeth Costner Dallas, US 20 28
West, Jeffrey Alan Plano, US 58 465
Williams, Byron Lovell Plano, US 54 255

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