Multi-Gate Device And Related Methods
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Apr 4, 2024
app pub date -
Dec 1, 2023
filing date -
Feb 27, 2020
priority date (Note) -
Published
status (Latency Note)
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Importance

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Abstract
A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
First Claim
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Family
Country | kind | publication No. | Filing Date | Type | Sub-Type |
---|---|---|---|---|---|
US | B2 | US11328963 | Jul 30, 2020 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT AS SECOND PUBLICATION | Multi-gate device and related methods | May 10, 2022 | |||
CN | A | CN113113296 | Feb 22, 2021 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
UNEXAMINED APPLICATION FOR A PATENT FOR INV. | Method for manufacturing semiconductor device | Jul 13, 2021 | |||
TW | A | TW202139264 | Feb 23, 2021 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
LAID OPEN APPLICATION FOR PATENT OR PATENT OF ADDITION | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE | Oct 16, 2021 | |||
US | B2 | US11854908 | May 09, 2022 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT AS SECOND PUBLICATION | Multi-gate device and related methods | Dec 26, 2023 |
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD | NO 8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
CHIANG, Kuo-Cheng | Hsinchu County, TW | 533 | 619 |
# of filed Patents : 533 Total Citations : 619 | |||
JHAN, Yi-Ruei | Keelung City, TW | 59 | 38 |
# of filed Patents : 59 Total Citations : 38 | |||
JU, Shi Ning | Hsinchu City, TW | 209 | 1001 |
# of filed Patents : 209 Total Citations : 1001 | |||
LIN, Zhi-Chang | Hsinchu County, TW | 162 | 353 |
# of filed Patents : 162 Total Citations : 353 | |||
PAN, Kuan-Ting | Taipei City, TW | 137 | 285 |
# of filed Patents : 137 Total Citations : 285 | |||
SU, Huan-Chieh | Changhua County, TW | 209 | 239 |
# of filed Patents : 209 Total Citations : 239 | |||
WANG, Chi-Hao | Hsinchu County, TW | 2 | 4 |
# of filed Patents : 2 Total Citations : 4 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Oct 4, 2027 |
7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Oct 4, 2031 |
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Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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