CAPTURING OF ON-CHIP RESETS IN AN INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Apr 4, 2024
app pub date -
Oct 4, 2022
filing date -
Oct 4, 2022
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status (Latency Note)
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Abstract
A system includes a first reset capture register configured to receive a plurality of reset signals, a last reset capture register configured to receive the plurality of reset signals, and a reset control circuit. The reset control circuit is configured to perform a startup procedure in response to assertion of a first reset signal of the plurality of rest signals. The startup procedure beings with a start state and ends in an active state in which the system operates in normal operation, and the first reset signal is asserted while the system is in the active state. The first reset capture register is configured to capture a first state of the plurality of reset signals in response to assertion of the first reset signal, and the last reset capture register is configured to capture a final state of the plurality of reset signals prior to completing the startup procedure.
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