SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH INPUT-DEPENDENT LEAST SIGNIFICANT BIT (LSB) SIZE
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Mar 21, 2024
app pub date -
Sep 20, 2022
filing date -
Sep 20, 2022
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Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.
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