SEMICONDUCTOR PROCESSING APPARATUS AND METHOD UTILIZING ELECTROSTATIC DISCHARGE (ESD) PREVENTION LAYER
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Mar 14, 2024
app pub date -
Nov 21, 2023
filing date -
Apr 17, 2019
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Abstract
Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
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