Low-power pulse output circuit

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11949409
APP PUB NO 20240063786A1
SERIAL NO

18151477

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Abstract

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A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.

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Patent Owner(s)

Patent OwnerAddress
WENZHOU UNIVERSITY325035 WENZHOU CITY NATIONAL UNIVERSITY SCIENCE PARK INCUBATOR NO 38 DONGFANG SOUTH ROAD OUHAI DISTRICT WENZHOU ZHEJIANG WENZHOU CITY ZHEJIANG PROVINCE 325035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Gang Zhejiang, CN 629 4192
Li, Xiangyu Zhejiang, CN 57 50
Wang, Pengjun Zhejiang, CN 65 90

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