FREQUENCY LOCKED LOOP CIRCUIT AND CLOCK SIGNAL GENERATION METHOD
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United States of America Patent
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Issued Date -
Feb 15, 2024
app pub date -
Oct 29, 2023
filing date -
Dec 26, 2019
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Abstract
A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.
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