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Abstract

In a layout alignment method of a lithographic system for semiconductor device processing, a reference pattern that is included in a reference pattern module is disposed over an alignment pattern of a substrate. The alignment pattern includes two or more sub-patterns that extend in a first interval along a first direction and are arranged with a first pitch in a second direction. Each sub-pattern includes first patterns and second patterns. A width of the first pattern is at least twice as wide as a width of the second pattern. The reference pattern at least partially overlap with the alignment pattern. An overlay alignment error between the reference pattern and the alignment pattern of the substrate is determined. When the overlay alignment error is not more than a threshold value, a photo resist pattern is produced on the substrate based on the layout pattern associated with reference pattern.

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First Claim