EEG IMPEDANCE TEST CIRCUIT, METHOD, AND DEVICE
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United States of America Patent
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Issued Date -
Feb 15, 2024
app pub date -
Dec 27, 2022
filing date -
Aug 12, 2022
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Abstract
Disclosed are an EEG impedance test circuit, a method, and a device. The circuit comprises a frequency selecting circuit, an amplification circuit, a follower circuit, and a power supply terminal AVCC. An input end of the frequency selecting circuit is connected to the power supply terminal AVCC, the input end of the frequency selecting circuit is further connected to the input end of the amplification circuit, an output end of the frequency selecting circuit is connected to the output end of the amplification circuit, and the output end of the amplification circuit is connected to the input end of the follower circuit; the frequency selecting circuit is configured for oscillating so as to generate an oscillation signal; and the follower circuit is configured for isolating the frequency selecting circuit and the amplification circuit; the follower circuit is configured for circuit isolation.
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