Semiconductor Package or a Printed Circuit Board, Both Modified to One or More of Reduce, Inverse or Utilize Magnetic Coupling Caused by the Load Current of a Semiconductor Transistor
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United States of America Patent
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Issued Date -
Jan 11, 2024
app pub date -
Jun 30, 2023
filing date -
Jul 6, 2022
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Abstract
A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.
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