Method of forming high-voltage transistor with thin gate poly

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United States of America Patent

PATENT NO 12029041
APP PUB NO 20240008279A1
SERIAL NO

18214072

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Abstract

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A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

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Patent Owner(s)

Patent OwnerAddress
INFINEON TECHNOLOGIES LLC198 CHAMPION COURT SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Kuo Tung Saratoga, US 40 89
Chen, Chun San Jose, US 197 1251
Kang, Inkuk San Jose, US 27 319
Kang, Sung-Taeg Palo Alto, US 102 1106
Kim, Unsoon San Jose, US 60 524
Pak, James Sunnyvale, US 22 151

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