IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION
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United States of America Patent
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Issued Date -
Dec 21, 2023
app pub date -
Apr 19, 2023
filing date -
May 25, 2022
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Abstract
An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.
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