Clock frequency limiter
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United States of America Patent
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Jun 25, 2024
Grant Date -
Nov 23, 2023
app pub date -
May 20, 2022
filing date -
May 20, 2022
priority date (Note) -
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Abstract
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.
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