PHASE LOCK LOOP (PLL) SYNCHRONIZATION
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United States of America Patent
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Issued Date -
Nov 23, 2023
app pub date -
Jul 24, 2023
filing date -
May 14, 2019
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Abstract
In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.
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