Treating multiple cache lines as a merged cache line to store multiple blocks of data

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United States of America Patent

PATENT NO 11947460
APP PUB NO 20230342298A1
SERIAL NO

17729233

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Abstract

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Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

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Patent Owner(s)

Patent OwnerAddress
ARM LIMITED110 FULBOURN ROAD CAMBRIDGESHIRE CAMBRIDGE CB1 9NJ

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Antonov, Anton Cambridge, GB 10 88
Bull, David Michael Cambridge, GB 62 429
Rezard, Vincent Vence, FR 8 43
Vasekin, Vladimir Cambridge, GB 32 309

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