RADAR RECEIVER
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United States of America Patent
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Issued Date -
Sep 28, 2023
app pub date -
Mar 13, 2023
filing date -
Mar 24, 2022
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Abstract
A radar receiver comprising: an ADC (510) that samples analogue intermediate frequency, IF, signalling in order to generate digital signalling, wherein the digital signalling comprises a plurality of digital-values; a digital processor that populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis; and a sampling-rate-adjuster that is configured to set a sampling rate associated with the bin-values in the 2-dimensional array based on an index of the slow time axis. The digital processor also performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.
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