Techniques for Scalable Load Balancing of Thread Groups in a Processor

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United States of America Patent

APP PUB NO 20230289211A1
SERIAL NO

17691872

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Abstract

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A processor supports new thread group hierarchies by centralizing work distribution to provide hardware-guaranteed concurrent execution of thread groups in a thread group array through speculative launch and load balancing across processing cores. Efficiencies are realized by distributing grid rasterization among the processing cores.

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Patent Owner(s)

Patent OwnerAddress
NVIDIA CORPORATION2788 SAN TOMAS EXPRESSWAY SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DASH, Rajballav San Jose, US 7 30
DEB, Shayani Seattle, US 4 8
GOVIL, Naman Sunnyvale, US 3 7
HIROTA, Gentaro San Jose, US 18 397
KRASHINSKY, Ronny Portola Valley, US 21 59
LONG, Ze San Jose, US 24 34
MANDAL, Tanmoy Saratoga, US 6 61
MEI, Chen Shanghai, CN 2 4
PHARRIS, Brian Cary, US 9 27
STEPHANO, Kevin San Francisco, US 1 3
TUCKEY, Jeff Saratoga, US 9 30

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