Chip-on-wafer-on-substrate package with improved yield

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 12068300
APP PUB NO 20230275077A1
SERIAL NO

17680523

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Abstract

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A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDHSIN-CHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Chia-Wei Taipei, TW 186 1465
Chen, Ju-Min Tainan, TW 3 0
Chuang, Yao-Chun Hsinchu, TW 94 790
Wu, Jyun-Lin Hsinchu, TW 13 46

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