CHIP RELIABILITY TEST ASSEMBLY

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20230258710A1
SERIAL NO

17836744

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The present invention proposes a chip reliability test assembly, which comprises a motherboard and a daughter board. The motherboard is used to support the chips during an aging acceleration process at high temperature. The daughter board is used to measure the electricity of chip after the aging acceleration process. Each chip holder is removable off the motherboard. The daughter board does not go through the aging acceleration process and can be reusable.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
LUXSENTEK MICROELECTRONICS CORP5F NO 119 BAOZHONG RD XINDIAN DIST NEW TAIPEI CITY

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
HO, YUEH-HUNG New Taipei City, TW 3 0
HSI, CHEN-HUA New Taipei City, TW 13 13
HSIAO, CHAO-YANG New Taipei City, TW 6 28
LEE, SHENG-CHENG New Taipei City, TW 21 26
LIN, CHIH-WEI New Taipei City, TW 359 5145
LIN, WEN-SHENG New Taipei City, TW 104 920

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation