DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
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United States of America Patent
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Issued Date -
Aug 10, 2023
app pub date -
Aug 15, 2022
filing date -
Feb 7, 2022
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Abstract
In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.
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