Method for performing divided-clock phase synchronization in multi-divided-clock system, synchronization control circuit, synchronization control sub-circuit, and electronic device
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United States of America Patent
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Aug 22, 2023
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Jul 20, 2023
app pub date -
Oct 27, 2022
filing date -
Jan 14, 2022
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Abstract
A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.
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