Fractional phase locked loop (PLL) with digital control driven by clock with higher frequency than PLL feedback signal
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United States of America Patent
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Sep 19, 2023
Grant Date -
Jun 1, 2023
app pub date -
Nov 29, 2021
filing date -
Nov 29, 2021
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Abstract
A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.
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