Memory device and forming method thereof
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United States of America Patent
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Aug 13, 2024
Grant Date -
Jun 1, 2023
app pub date -
Apr 7, 2022
filing date -
Nov 26, 2021
priority date (Note) -
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Abstract
A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.
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