CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL

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United States of America Patent

APP PUB NO 20230170388A1
SERIAL NO

18095720

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Abstract

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Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

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Patent Owner(s)

Patent OwnerAddress
DAEDALUS PRIME LLCBRONXVILLE NY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cea, Stephen M Hillsboro, US 129 2958
Ghani, Tahir Protland, US 756 7842
Glass, Glenn A Portland, US 182 5017
Kennel, Harold W Portland, US 61 264
Kotlyar, Roza Portland, US 55 855
Kuhn, Kelin J Aloha, US 90 2639
Murthy, Anand S Portland, US 351 6235

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