CLOCK SIGNAL GENERATION CIRCUIT
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United States of America Patent
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Issued Date -
May 4, 2023
app pub date -
Oct 18, 2022
filing date -
Oct 29, 2021
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Abstract
The present invention provides a clock signal generation circuit including a global PLL and a plurality of local PLLs. In the operation of the clock signal generation circuit, the global PLL is configured to receives a reference clock signal to generate a synchronization clock signal, and the plurality of local PLLs receive the synchronization clock signal to generate a plurality of clock signals, respectively, and the plurality of clock signals are used to generate a plurality of output clock signals.
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