Signal processing circuit and reception device
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United States of America Patent
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Jul 16, 2024
Grant Date -
Mar 23, 2023
app pub date -
Mar 11, 2022
filing date -
Sep 17, 2021
priority date (Note) -
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status (Latency Note)
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Abstract
According to an embodiment, a shift register parallelizes a serial data signal serving to transfer data including multiple symbols on the basis of a first clock. A first circuit generates, on the basis of the first clock, a second clock being a clock signal for transferring a parallel data signal having a width of the first number of bits. A first flip-flop group sequentially fetches data of the first number of bits from the serial data signals parallelized by the shift register on the basis of the second clock. The first flip-flop group then outputs the fetched data of the first number of bits as a parallel data signal. A second circuit adjusts a phase of the second clock such that the first flip-flop group fetches data of the first number of bits beginning with bit data located at a head of each symbol of the multiple symbols.
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