CHIPSET FOR FRAME RATE CONTROL AND ASSOCIATED SIGNAL PROCESSING METHOD
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United States of America Patent
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Issued Date -
Feb 16, 2023
app pub date -
May 9, 2022
filing date -
May 9, 2022
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.
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