POWER DEVICE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Feb 16, 2023
app pub date -
May 5, 2022
filing date -
May 5, 2022
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Abstract
A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.
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