LOGIC CIRCUIT DESIGN METHOD
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United States of America Patent
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Issued Date -
Feb 2, 2023
app pub date -
Dec 9, 2020
filing date -
Dec 9, 2020
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Abstract
Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.
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