Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors
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United States of America Patent
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Feb 28, 2023
Grant Date -
Dec 1, 2022
app pub date -
May 31, 2021
filing date -
May 31, 2021
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Abstract
A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
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