Detecting Possible Security Violations In An Integrated Circuit
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United States of America Patent
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Issued Date -
Sep 29, 2022
app pub date -
Mar 24, 2021
filing date -
Mar 24, 2021
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Abstract
In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.
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