Nonvolatile semiconductor storage device and read voltage correction method
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United States of America Patent
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Dec 26, 2023
Grant Date -
Aug 11, 2022
app pub date -
Feb 4, 2022
filing date -
Feb 8, 2021
priority date (Note) -
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Abstract
A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.
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