Phase-locked loop circuit and digital operation system
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United States of America Patent
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Sep 12, 2023
Grant Date -
Jul 21, 2022
app pub date -
Dec 30, 2019
filing date -
Apr 29, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.
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