Calibration of parametric error of digital-to-time converters
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United States of America Patent
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Apr 18, 2023
Grant Date -
Jul 14, 2022
app pub date -
Jan 11, 2022
filing date -
Jan 12, 2021
priority date (Note) -
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Abstract
In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.
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