CLOCKING ARCHITECTURE FOR A MULTI-DIE PACKAGE
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United States of America Patent
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Issued Date -
Jul 14, 2022
app pub date -
Apr 1, 2022
filing date -
Apr 1, 2022
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Abstract
A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.
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