MEMORY TRANSACTION QUEUE BYPASS BASED ON CONFIGURABLE ADDRESS AND BANDWIDTH CONDITIONS
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United States of America Patent
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Issued Date -
Jun 9, 2022
app pub date -
Feb 28, 2022
filing date -
Feb 28, 2022
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Abstract
An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.
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