PARALLELIZATION AND PIPELINING STRATEGIES FOR AN EFFICIENT ANALOG NEURAL NETWORK ACCELERATOR
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United States of America Patent
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May 19, 2022
app pub date -
Nov 15, 2021
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Nov 15, 2021
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Abstract
Parallelization and pipelining techniques that can be applied to multi-core analog accelerators are described. The techniques descried herein improve performance of matrix multiplication (e.g., tensor-tensor multiplication, matrix-matrix multiplication or matrix-vector multiplication). The parallelization and pipelining techniques developed by the inventors and described herein focus on maintaining a high utilization of the processing cores. A representative processing systemin includes an analog accelerator, a digital processor, and a controller. The controller is configured to control the analog accelerator to output data using linear operations and to control the digital processor to perform non-linear operations based on the output data.
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