GRAPH REORDERING AND TILING TECHNIQUES

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United States of America Patent

APP PUB NO 20220156322A1
SERIAL NO

17533976

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Abstract

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Graph reordering and tiling techniques are described herein. In one example, large graphs (e.g., for inferencing with graph neural networks) can be reordered, tiled, or both, to achieve maximal data reuse and uniform compute load distribution. In one example, a reordering method involves performing breadth first search (BFS) renumbering on a graph data set with the highest degree destination node as the root node to generate a reordered graph data set. BFS is then performed again with candidate nodes from the last level of the reordered graph. The second reordered graph data set with the lowest bandwidth or best profile can be selected for further processing. In one example, a method of tiling involves dividing a graph data set into tiles to balance expected compute time.

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Patent Owner(s)

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INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
BAIREDDY, Vijayavardhan Hyderabad, IN 7 51
MAKKADAYIL, Srajudheen Bangalore, IN 5 7
MISHRA, Bakshree Bhubaneswar, IN 3 3
SINGH, Tarjinder Bangalore, IN 4 15
SR, Sridhar Bangalore, IN 2 1
SUMIRAN, Ranga Bengaluru, IN 1 1
THYAGARAJAN, Vidhya Bangalore, IN 6 33

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