STACKED SOLID ELECTROLYTIC CAPACITOR, INTEGRATED CIRCUIT PRODUCT AND ELECTRONIC PRODUCT
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United States of America
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Issued Date -
May 5, 2022
app pub date -
Nov 2, 2021
filing date -
Nov 2, 2021
priority date (Note) -
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Abstract
A stacked solid electrolytic capacitor is provided in the present disclosure. The stacked solid electrolytic capacitor includes a capacitive module, a conductive module and a packaging structure. The capacitive module includes capacitive units stacked up sequentially. The conductive module includes a positive terminal, a negative terminal and at least one anti-oxidizing layer. The positive terminal is electrically connected to one of the capacitive units. The negative terminal is electrically connected to the one of the capacitive units through a conductive paste layer. The at least one anti-oxidizing layer is arranged between the negative terminal and the conductive paste layer. The packaging structure surrounds the capacitive module and the conductive module. Therefore, it is difficult for an oxide layer forming between the negative terminal and the capacitive units, and the equivalent series resistance of the stacked solid electrolytic capacitor can be reduced.
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