PHYSICAL LAYER LOW-LATENCY FORWARD ERROR CORRECTION

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20220123860A1
SERIAL NO

17071843

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Abstract

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Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques minimize latency in the PHY, being optimal for Gen-Z systems. The FEC techniques can provide improvements over existing FEC schemes that employ large code word sizes and experience high latency.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP11445 COMPAQ CENTER DR W HOUSTON TX 77070

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
BRUEGGEN, CHRISTOPHER MICHAEL Plano, US 6 29
CHOBANYAN, ELENE Ft. Collons, US 10 15
REGAN, JAMES DONALD Ft. Collins, US 3 4

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